The present invention relates to a semiconductor device, and more specifically to an 1-transistor type DRAM cell, a DRAM device and a DRAM comprising thereof and a driving method thereof and a manufacturing method thereof.
A semiconductor device such as a DRAM is generally integrated on a silicon wafer. However, for the silicon wafer used in the semiconductor device, the whole silicon is not used in the operation of the device but only the silicon limited to the thickness of several μm from the surface thereof is used in the operation of the device. After all, the remaining silicon wafer excepting a portion required in the operation of the device becomes a factor increasing power consumption and decreasing driving speed.
Therefore, the necessity of a silicon on insulator (SOI) wafer constituted by forming a silicon single crystal layer of a thickness of several μm by interposing an isolating layer on the silicon substrate has become an issue and the semiconductor device integrated on the SOI wafer is capable of being operated at a high speed by means of less junction capacity and at a low-voltage by means of the a low threshold voltage, as compared to the semiconductor device integrated on a general silicon wafer. Such a semiconductor device integrated on the SOI wafer has been reported.
FIG. 1 is cross-sectional view showing a DRAM cell implemented on a SOI wafer of the prior art. In FIG. 1, a SOI wafer 10 is formed in a stacked structure of a silicon substrate 1, a buried oxide film 2, and a silicon layer 3, and a device isolating layer 11 defining an active region on the silicon layer 3 of such a SOI wafer 10 is formed to contact the buried oxide film 2, wherein in the upper of the active region of the silicon layer 3 a gate 12 is formed and source/drain regions 13a and 13b are formed to contact the buried oxide film 2 within the silicon layers 3 on both sides of the gate 12.
In the DRAM cell implemented on the SOI wafer 10, data store is made by means of holes and electrons captured by a floating body corresponding to a channel region below the gate 12.
For example, as shown in FIG. 2a, a store “1” state can be appreciated as the state where there are a few holes in the floating body, and as shown in FIG. 2b, a store “0” state can be appreciated as the state where there are few hole in the floating body or there are a few electrons therein. And, in a read state, the more amount of sensing current flows when an 1-transistor type cell is in the store “1” than in the store “0”.
FIG. 3 is a graph showing a cell read current when a cell drain voltage Vd is 0.2V, a cell source voltage is ground GND and a cell gate voltage is swept, for a DRAM cell implemented on a SOI wafer of the prior art.
As shown, current is largest in a store “1” state, current is smallest in a store “0” state, and a reference voltage is positioned in the intermediate therebetween.
As described above, there is a problem that a driving method of a floating body type 1-transistor type DRAM cell capable of efficiently writing and reading data in a low voltage state should be proposed.
Also, there is a further problem that a method capable of stably driving a SOI 1-transistor type DRAM cell and a cell array thereof should be proposed.
Also, when implementing a semiconductor device applying the SOI wafer, there is an advantage of the device characteristics as described above, however, the SOI wafer is more expensive than a general silicon wafer so that it is not preferable in view of productivity.
In particular, when manufacturing a semiconductor device using the SOI wafer, the existing equipments and processes are designed to be suitable for the case applying the silicon wafer so that the modification of the manufacturing equipments and processes and the development thereof are also required. Therefore, it is substantially difficult to use the manufacturing of the semiconductor device applying the SOI wafer.